<Related Technique 1>
Related techniques of a semiconductor device including a group III nitride semiconductor as a principal raw material will be described in the below. FIG. 11 is a diagram illustrating schematically a cross-section of a normally-off type field effect transistor exploiting the group III nitride semiconductor according to Related Technique 1. Such a field effect transistor is disclosed, for example, in Patent Literature 1. In Patent Literature 1, there is disclosed a normally-off type GaN based field effect transistor (FET) of a HEMT (High Electron Mobility Transistor) structure that has a very small on-resistance when operating and that is capable of operating on a large current. It is noted that FIG. 11 is a drawing re-drafted in this application based on FIG. 1 and so on of Patent Literature 1. Referring to FIG. 11, the field effect transistor of the Related Technique 1 has a following arrangement:
A substrate 110 is a sapphire substrate which is a (0001) plane substrate, that is, a C-face substrate;
a buffer layer 111 is formed of GaN or AlGaN;
a channel layer 113 is formed of GaN; and
an electron supplying layer 114 is formed of AlGaN.
On the electron supplying layer 114 that is an upper most semiconductor layer, a source electrode 121 and a drain electrode 122 are disposed to be spaced to each other. Each of the source and drain electrodes 121 and 122 has ohmic contact to the electron supplying layer 114.
A semiconductor surface located between the source electrode 121 and the drain electrode 122 is covered by a SiN protective film 131. The protective film 131 has an opening formed in a part thereon and a groove-shaped recess 141 is formed in a semiconductor portion lying directly underneath the opening in the protective film 131.
There is arranged a gate insulating film 132, formed of Al2O3, for example, to cover sides and a bottom surface of the recess 141. A gate electrode 123 is arranged on the gate insulating film 132.
In the channel layer 113 on a heterojunction interface between the channel layer 113 and the electron supplying layer 114, there is generated a two-dimensional electron gas (2DEG) 151. However, in a location of a channel layer in which the gate insulating film 132 is arranged in place of the electron supplying layer 114 (recess 141) and the electron supplying layer 114 is not provided, no two-dimensional electron gas is generated. That is, spreading of the two-dimensional electron gas 151 in two-dimensional directions is interrupted at a location where the gate insulating film 132 is arranged. Thus, when the gate is opened, a drain current (drain-to-source current) flowing through the channel layer 113 is suppressed. When a pre-set bias voltage is applied to the gate electrode 123, an inverted population layer of electrons is formed at a location of the channel layer 113 directly underneath the gate insulating film 132. The two-dimensional electron gas, which was interrupted before applying the gate voltage, is connected via the inverted population layer, thus exhibiting an operation (FET operation) of a field effect transistor (a normally-off type FET).
FIG. 12 is a diagram illustrating an energy-band underneath a gate in an equilibrium state of the semiconductor device illustrated in FIG. 11. When a positive voltage is applied to the gate electrode, there occurs a state in which the Fermi level of the semiconductor is higher than a conduction band, so that electrons are accumulated in an interface between an insulation film and the semiconductor. A gate voltage, in which such a state is produced, is termed a ‘threshold voltage’, which is one of crucial indices of a field effect transistor.
In particular, in the case where a normally off transistor is used as a switching device for power control, a threshold voltage greater than or equal to +3V is required in order to secure safety which takes account of noise immunity.    Patent Literature 1: International Laid-Open Gazette of 2003/071607 (WO2003/071607)    Patent Literature 2: International Laid-Open Gazette of 2009/081584 (WO2009/081584)    Non-Patent Literature 1: Journal of Physics, vol. 14, pp. 3399 to 3434, 2002